Fin field-effect transistor (FinFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. Known FinFET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to a substrate) between source/drain regions at opposite ends of the fins in the horizontal direction. As horizontal devices are scaled down, there is reduced space for metal gate and source/drain contacts, which leads to degraded short-channel control and increased middle of the line (MOL) resistance.
Vertical field-effect transistors (VFETs) (also referred to as vertical transport field effect transistors (VTFETs)) are becoming viable device options for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to 5 nanometer (nm) node and beyond. VFET devices include fin channels with source/drain regions at ends of the fin channels on top and bottom sides of the fins. Current runs through the fin channels in a vertical direction (e.g., perpendicular to a substrate), for example, from a bottom source/drain region to a top source/drain region. Vertical transport architecture devices are designed to address the limitations of horizontal device architectures in terms of, for example, density, performance, power consumption, and integration by, for example, decoupling gate length from the contact gate pitch, providing a FinFET-equivalent density at a larger contacted poly pitch (CPP), and providing lower MOL resistance.
In current VFET design, the distance from source/drain contacts to fin tips is relatively large due to concerns regarding overlays and shorts between gate and source/drain contacts, which results in an unwanted increase in device size or unwanted reductions in fin length.